Integrated circuit arrangement with intermediate materials and associated components

ABSTRACT

An integrated circuit arrangement having a metallization layer, an interconnect dielectric, electrically conductive interconnect intermediate material, electrically conductive connecting sections, connecting section dielectric between the connecting sections, and connecting section intermediate material. The metallization layer contains electrically conductive interconnects between which the interconnect dielectric is disposed. The electrically conductive interconnect intermediate material is arranged between a side area of an interconnect and the interconnect dielectric. The electrically conductive connecting sections in each case form a section of an electrically conductive connection to or from an interconnect and the connecting section dielectric is between the connecting sections. The connecting section intermediate material is arranged in each case between a connecting section and the connecting section dielectric and/or between a connecting section and an interconnect. The interconnect intermediate material and the connecting section intermediate material make contact with one another at at least one connection.

This application is the national stage application of internationalapplication number PCT/DE03/02741, filed on Aug. 14, 2003, which claimsthe benefit of priority to German Patent Application 102 41 154.9, filedon Sep. 5, 2002, incorporated herein by reference.

The invention relates to an integrated circuit arrangement containing atleast one metallization layer. A multiplicity of electrically conductiveinterconnects, for example made of copper or made of aluminum, arearranged in the metallization layer. Arranged between the interconnectsof the metallization layer is an interconnect dielectric, for examplesilicon dioxide or a material having a dielectric constant ofsignificantly less than four. An electrically conductive interconnectintermediate material, which differs from the material of theinterconnect, is in each case arranged between a side area of aninterconnect that is situated transversely with respect to themetallization layer in the metallization layer and the interconnectdielectric.

The integrated circuit arrangement additionally contains a multiplicityof electrically conductive connecting sections, for example so-calledvias, which in each case form a section—adjacent to the interconnect—ofan electrically conductive connection to or from an interconnect. By wayof example, the connecting sections comprise tungsten or copper.Arranged between the connecting sections is a connecting sectiondielectric having for example the same material composition as theinterconnect dielectric. A connecting section intermediate material isarranged between a connecting section and the connecting sectiondielectric and/or between a connecting section and an interconnect.

The intermediate materials are also referred to as liners, inter alia,and fulfill for example at least one of the following functions:

-   -   formation of a metallurgical barrier layer,    -   formation of a diffusion barrier,    -   increasing the adhesive force of the interconnect or of the        connecting section in the dielectric,    -   compensation of material stresses.

Suitable materials for the intermediate material are for example therefractory metals molybdenum, tungsten, tantalum and titanium. Inparticular, however, the nitrides of said metals are also used asintermediate material, if appropriate also in double layers ormultilayers, e.g. titanium/titanium nitride.

It is an object of the invention to specify an integrated circuitarrangement which is constructed in a simple manner and has improvedelectrical properties in comparison with known circuit arrangements, inparticular an increased reliability and/or service life. Moreover, theintention is to specify an associated method for generating design datafor the production of this circuit arrangement, an associated programand an associated data processing system.

The invention is based on the consideration that the resistance of theconnecting section/interconnect system to electromigration but also tostress migration and thermocycling robustness depend to a very greatextent on the arrangement of the intermediate materials with respect toone another. By way of example, if the connecting section intermediatematerial is arranged at a distance from the interconnect intermediatematerial, then there is no redundancy through the intermediate materialin the conduction of the current. In the case of a hole formation (void)in the region of the contact of connecting section and interconnect as aresult of electromigration or else stress migration, the intermediatematerial is not available as a redundant current path. Consequently,even small vacancy volumes lead to a large resistance increase in thecontact resistance between interconnect and connecting section and canconsiderably impair the function of the integrated circuit. The circuitarrangement can even fail.

Therefore, in the case of the circuit arrangement according to theinvention, at at least one connection, the interconnect intermediatematerial makes contact with the connecting section intermediate materialfor example at an edge of the interconnect. The contact between theintermediate materials produces a current path redundancy which enableslonger operation of the integrated circuit arrangement even withelectromigration remaining the same.

In one development of the circuit arrangement, at the connection, theinterconnect intermediate material and the connecting sectionintermediate material make contact at two or three or four side areas oredges of an interconnect. At interconnects at which the connectingsection or the via is connected to the interconnect intermediatematerial at two, three or four side areas or edges, the currentconductivity is significantly higher than in comparison witharrangements without a contact location or with only one contactlocation or a small contact region of connecting section intermediatematerial and interconnect material. A cause of this is the “barrierredundancy”. Even with insipient formation of vacancies below or abovethe connecting section as a result of electromigration or stressmigration, the current still flows via the electrically conductiveintermediate material. An appreciable increase in resistance resultingin a functional disturbance or the failure of the circuit arrangementoccurs only in the case of a comparatively large vacancy volume, i.e. inthe case of a correspondingly higher current loading or a longeroperating duration in comparison with structures without or with reducedintermediate material redundancy.

The contact of two side areas or edges can be achieved if the connectingarrangement is arranged in a corner of a covering area or an otherwiseliner-free bottom area of the interconnect or if the interconnect andthe connecting section have approximately the same extent in the lateraldirection. The contact of three side areas or edges is made possible ifthe connecting section and the interconnect have the same extent in thelateral direction and if the connecting section is arranged at the endof the interconnect. A contact of four side areas or edges is possiblewhen the connecting section and the interconnect in each case have thesame dimensions in two directions that are at right angles to oneanother. Such dimensions are expedient for example in the case ofconnecting sections that are stacked one above the other and penetratethrough a plurality of metallization layers. In each metallization layerthere are so-called connection plates with a square or rectangular basicarea for connecting the connecting sections.

In a next development, the interconnect has a constriction at theconnecting section, the width of said constriction being chosen in onerefinement such that contact regions are produced at opposite side areasof the interconnect. The constriction can be dimensioned to becomparatively short in comparison with the total length of aninterconnect. Thus, in one refinement, the constriction, along thelongitudinal axis of the interconnect, has a length that is less thanfive times or even less than three times the width of the constrictionat its narrowest location. The use of constrictions is a simplepossibility for increasing the number of contact regions of theintermediate materials.

In one development of the circuit arrangement with constriction, theconnecting section is arranged at the end of the interconnect. Theconstriction has the form of a wedge or the form of a step.

In an alternative development of the circuit arrangement withconstriction, the interconnect extends in at least two differentdirections from the connecting section. The constriction has, at itsends, in each case the form of a wedge or the form of a step. In thecase of constrictions within an interconnect, particular considerationis to be given to secondary effects, such as e.g. current concentration.In order to avoid local current spikes in the case of the currentconcentration that is unavoidable due to the constriction, theinterconnect is not constricted abruptly at angles of ninety degrees,for example, but rather gradually.

In a next development, at least two sections of the same interconnect orof different interconnects are wider than the connecting sections atconnecting sections. The contact regions of the intermediate materialsare situated at such side areas of the interconnect sections whosenormal directions are situated transversely or oppositely with respectto one another. This requires arrangement of the connecting sections ina targeted manner at side areas with a normal direction that differsfrom one another.

In a further aspect, the invention relates to a method for generatingdesign data for the production of integrated circuit arrangements, inparticular of the circuit arrangement according to the invention or oneof its developments. In the case of the method according to theinvention, design data and rules for altering the design data arepredefined. An automatic application of the rules to the design data hasthe consequence that the number of contact locations of interconnectintermediate material and connecting section intermediate material isincreased in a targeted manner. The automatic application of the rulesmakes it possible to test, and if appropriate alter, the design at amultiplicity of connecting sections in a very short time. Ifappropriate, only sampling inspection by experienced developmentpersonnel is necessary.

In one development of the method, the rules comprise two fundamentalvariants for increasing the number of contact locations, namely:

-   -   local constriction of interconnects, and    -   displacement of interconnects or connecting sections, in one        refinement a displacement of interconnects also including a        shortening of the interconnect.

The invention additionally relates to a program and an apparatus, inparticular a data processing system, which are suitable for carrying outthe method according to the invention or one of its developments. Theabovementioned technical effects thus hold true for the method, for theprogram and for the apparatus.

Exemplary embodiments of the invention are explained below withreference to the drawings, in which:

FIG. 1 shows a via and an interconnect without a contact locationbetween the liner of the interconnect and the liner of the via,

FIGS. 2A to 2C show the production of local constrictions within aninterconnect in a design,

FIGS. 3A to 3C show the production of local constrictions at the end ofan interconnect in a design,

FIGS. 4A and 4B show the displacement of a via to the edge of aninterconnect in a design,

FIGS. 5A to 5C show the displacement of a via to an end edge of aninterconnect or into a corner of an interconnect covering area in adesign,

FIGS. 6A and 6B show the displacement of a via having the same width asan interconnect to the end of the interconnect in a design,

FIG. 7 shows a design for an arrangement with quadruple liner contact,

FIG. 8 shows method steps for increasing the contact locations of linersin a targeted manner, and

FIG. 9 shows an apparatus for performing the method.

FIG. 1 shows a detail from an integrated circuit arrangement 10containing a via 12 and an interconnect 14. Associated with theintegrated circuit arrangement 10 are design data which have not yetbeen processed with the aid of a method for increasing the number ofcontact locations of liners in a targeted manner.

The integrated circuit arrangement 10 contains a metallization layer 16extending essentially in a plane that lies parallel to the surface of asemiconductor substrate (not illustrated) in which a multiplicity ofintegrated semiconductor components are arranged, e.g. FET transistors(field effect transistor). The metallization layer 16 contains, besidesthe interconnect 14, a multiplicity of other interconnects (notillustrated) that are isolated from one another by a dielectric 18, forexample by silicon dioxide. In the exemplary embodiment, theinterconnects 14 of the metallization layer 16 comprise copper.

The metallization layer 14 has been produced with the aid of a so-calleddamascene or dual damascene method. In this method, the following stepsare performed in the order specified:

-   -   the dielectric 18 is deposited,    -   trenches for the interconnects 14 are etched,    -   an interconnect liner layer is deposited, which gives rise for        example to an interconnect liner 20 for the interconnect 14 at        the bottom and at the side areas of the trenches for the        interconnect 14 that are situated transversely in the        metallization layer 16 and thus later also at the bottom and the        side areas of the interconnect 14 that are situated transversely        with respect to the metallization layer 16. The interconnect        liner layer has for example a thickness of 5 nm, of 15 nm or of        20 nm,    -   the trenches for the interconnects 14 are filled with the        interconnect material, and    -   by means of a chemical mechanical polishing method, the filling        material and the liner material are removed again above the        trench edges, planarization being effected.

The metallization layer 16 is covered by a dielectric intermediate layer22, for example made of silicon nitride. Situated above the dielectricintermediate layer 22 is a dielectric layer 24 e.g. made of silicondioxide, in which a multiplicity of vias are arranged, for example thevia 12.

During the production of the via 12 and the other vies, firstly contactholes 26 were etched into the dielectric layer 24 and the dielectricintermediate layer 22. This means that there is no interconnect liner 20at a covering area remote form the bottom area of the interconnect 14. Avia liner layer was subsequently deposited, for example a via liner 28having been deposited in the contact hole 26. The via liner 28 alsocovers the bottom 30 of the contact hole 26. The bottom 30 o the contacthole 26 bears directly on a covering area of the interconnect 14 orpenetrates the interconnect 14 somewhat. By way of example, the via line28 has the same thickness as the interconnect liner 20. In the exemplaryembodiment, the liner material for the interconnect liner 20 and for thevia liner 28 is titanium nitride. The area of the interconnect 14 thatis adjacent to a connecting section 12 is essentially free and/or morethan 80% free of an electrically conductive intermediate material.

After the deposition of the via liner 28, the contact holes 26 werefilled with tungsten or copper, for example, the via 12 having beenproduced. Still further metallization layers are situated above thedielectric layer 24 in the exemplary embodiment.

FIG. 1 additionally illustrates a system 32 of coordinates having an xaxis 34, a y axis 36 and a z axis 38. The x-y plane lies parallel to theplanes in which lie the metallization layer 16, the dielectricintermediate layer 22 and the dielectric layer 24. The z directioncorresponds to the direction in which the metallization layer 16, thedielectric intermediate layer 22 and the dielectric layer 24 are stackedone above the other. The z direction thus corresponds to the directionof a normal to the surface of the semiconductor substrate.

As can readily be discerned in FIG. 1 on account of hatching of edgeareas of the interconnect liner 20 and of the via liner 28, interconnectliner 20 and via liner 28 do not make contact. It is possible, however,to produce such contact locations in the case of a covering area of theinterconnect 14 that is free of liners apart from the via liner, bymeans of the targeted alteration of the design data and a productionprocess based on the changed design data. By way of example, the via 12can be displaced in the y direction to the upper edge of a rear sidearea 40 of the interconnect 14, so that there is a contact location atan edge 42 of the interconnect 14. This and other possibilities forproducing contact locations are explained in more detail below withreference to FIGS. 2A to 7.

FIG. 2A shows a plan view of two planes of a design 48 for the patternsor structures of two masks for producing an integrated circuitarrangement and thus ultimately also for structures in two planes of theintegrated circuit arrangement itself. A system 50 of coordinates formsthe reference for design data for defining the designs and holds truefor the designs of FIGS. 2A to 3C. The system 50 of coordinates has an xaxis 52, a y axis 54 and a z axis 56. The designs in each case lie in anx-y plane. The system 50 of coordinates with regard to the designs thushas the same position as the system 32 of coordinates with regard to theintegrated circuit arrangement 10.

A design plane for the position of mask patterns for producinginterconnect trenches in a metallization layer lies opposite to the zdirection below a design plane for the position of mask patterns forproducing contact holes for vias. The position of edges of the trenchesis predefined with the aid of straight lines or lines in the lowerdesign plane. The position of the edges of contact holes is predefinedby circles in the upper design plane, see for example the straight lines58 and 60 for predefining the position of the edge of an interconnectand a circle 62 for predefining the position of a contact hole leadingto the interconnect. A width B1 between the straight lines 58 and 60that run parallel to one another, taking a scaling factor intoconsideration, defines the width of a trench for the interconnect. Adiameter D1 of the circle 62, taking the scaling factor intoconsideration, defines the diameter of the contact hole. In the design,the width B1 is approximately twice as large as the diameter D1. Thecircle 62 is centered between the two straight lines 60 and 58. FIG. 2Aadditionally illustrates a width B2, which, taking the scaling factorinto consideration, corresponds to the width of the interconnect liner.The width B2 amounts for example to a tenth of the width B1. Dashedlines 64 and 66 specify the position of the inner edge of theinterconnect liner with regard to the design 48.

FIG. 2B shows a design 70, which has been automatically produced fromthe design explained with reference to FIG. 2A with the aid of a methodexplained in more detail below with reference to FIG. 8. In the design70, there is a constriction 72 at lines 58 a and 60 a corresponding tothe straight lines 58 and 60. The constriction 72 is situated beneaththe circle 62, the position and diameter D1 of which have remainedunchanged. Steps are situated at the ends of the constriction 72. Theconstriction 72 has a length L1 that is approximately twice as large asthe diameter D1 of the circle 62. The constriction 72 has a constantwidth B3 along the entire length L1. The width B3 of the constriction 72is equal to the diameter D1. In a different exemplary embodiment, thewidth B3 is even less than the diameter D1. The circle 62 is centeredwith respect to the steps at the end of the constriction 72. A contactof the interconnect liner and of the via liner thus occurs in regionswhich, in the integrated circuit, will later have the same position asoverlap regions between the circle 62 and the interspace between thelines 58 a and 64 a and between the lines 60 a and 66 a. The dashedlines 64 a and 66 a correspond to the dashed lines 64 and 66 and specifythe position of the interconnect liner with regard to the design 70.

FIG. 2C shows an alternative alteration of the design data in accordancewith FIG. 2A, a constriction 82 with ends running in wedge-shapedfashion having been produced in a design 80. The position and thediameter of the circle 62 have remained unchanged. However, the positionof the lines 58 and 60 has been changed with the aid of simplegeometrical calculations such that lines 58 b and 60 b forming theconstriction 82 have been produced. Outside the constriction 82, thecourse of the lines 58 b and 60 b matches the course of the lines 58 and60. In the region of the constriction 82, the lines 58 b and 60 bfirstly continuously approach one another within a length L3, which issomewhat smaller than the diameter D1 of the circle 62. By way ofexample, if the interconnect is more than three times as wide as thediameter of the via, then in a different exemplary embodiment the lengthL3 is greater than D1.

Once the lines 58 b and 60 b have reached a distance from one anotherwhich corresponds to a width B4 having the same value as the diameter D1of the circle 62, then the lines 58 b and 60 b run parallel to oneanother for a length L2. The length L2 has a value that is approximatelyone and a half times the value of the diameter D1. Afterward, the lines58 b and 60 b run apart from one another again within a length L3. Theconstriction 83 again gives rise to overlap regions between the circle62 and the interspace between the line 58 b and a dashed line 64 b andbetween the line 60B and a dashed line 66 b. The dashed lines 64 b and66 b represent the position of the interconnect liner relative to thedesign 80.

The design illustrated in FIG. 2C produces, in the developed circuitarrangement, more favorable current concentration in the region of aconstriction of the interconnect that corresponds to the constriction82. In an alternative exemplary embodiment, the lines 58 b and 60 b donot change their direction abruptly, but rather continuously, therebyachieving an even more favorable current distribution.

FIG. 3A shows a design 90 with straight lines 92, 94 and 96 arranged inU-shaped fashion in a first design plane and with a circle 98overlapping the region surrounded by the straight lines 92 to 96. Thestraight lines 92 to 96 ultimately define the position of the edges oftrenches for an interconnect. The circle 98 ultimately defines theposition of a contact hole leading to the interconnect. A width B5between two straight lines 92 and 96 that run parallel to one anotherdefines the width of the trench, taking the scaling factor intoconsideration. The diameter D2 of the circle 98, taking the scalingfactor into consideration, defines the diameter of the contact hole. Thewidth B5 is approximately twice as large as the diameter D2. A dashedline 100 serves to represent the position of the inner edge of theinterconnect liner layer. The line 100 is at a distance B6 from the line92, 94 and 96, which distance amounts for example to approximately atenth of the width B5.

FIG. 3B shows a design 110 that was automatically produced from thedesign explained with reference to FIG. 3A with the aid of the methodexplained below with reference to FIG. 8. In the design 110, lines 114,116 and 118 correspond to the straight lines 92, 94 and 96 in the design90. In the design 110, there is a constriction 112 at the right-hand endof the lines 114 and 118. The constriction 112 is formed by the lines114 and 118 running symmetrically with respect to one another and hasstepped ends. At its narrowest location, the constriction 112 has awidth B7 corresponding to the diameter D2 of the circle 98. A length L4of the constriction 112 amounts to approximately one and half times thediameter D2. The position of the circle 98 in the design 110 hasremained unchanged with respect to the position of the circle 98 in thedesign 90. This means that the end side of the interconnect defined bythe straight line 94 has been displaced somewhat oppositely to the xdirection 52.

Whereas there are no contact regions between the interconnect liner andthe via liner in the case of an integrated circuit arrangement producedwith the aid of the design 90, there are three contact regions of vialiner and interconnect liner in the case of an interconnect/viaarrangement produced with the aid of the design 110. In the design 110,overlap regions 122, 124 and 126 between the circle 98 and a dashed line120, which corresponds to the line 100 and represents the position ofthe interconnect liner, correspond to the contact regions.

FIG. 3C shows a design 130 that has been produced from the design 90explained with reference to FIG. 3A upon application of an alternativerule with the aid of the method explained below with reference to FIG.8. The position of the circle 98 and its diameter D2 have remainedunchanged. However, a constriction 132 has been produced at lines 134,136 and 138 corresponding to the straight lines 92 to 96. Theconstriction 132 has a wedge-shaped section having a length L5. In theregion of the circle 98, the lines 134 and 138 are led parallel to oneanother over a length L6 until the straight line 136 is reached. Thevalue of the length L6 is approximately a fifth greater than the valueof the diameter D2. The length L5 is approximately half as large as thediameter D2 of the circle 98. A width B8 of the constriction 132 at itsnarrowest location is equal to the diameter D2.

An interconnect/via arrangement produced with the aid of the design 130also gives rise to three contact regions in overlap regions 140, 142 and144 between the circle 98 and a dashed line 146 indicating the positionof the interconnect liner.

FIG. 4A shows a design 150 with a straight line 152, which ultimatelypredefines the position of the edge of a trench for an interconnect. Adashed straight line 154 illustrates the position of an interconnectliner. A circle 156 is associated with another design plane andpredefines the position of a contact hole leading to the interconnect.The circle 156 is at a distance from the straight line 152 in the caseof which no overlap occurs between the circle 156 and the straight line152 or the straight line 154.

A system 160 of coordinates having an x axis 162, a y axis 164 and a zaxis 166 holds true for FIGS. 4A to 7. The statements made with respectto the system 50 of coordinates hold true with regard to the position ofdesign planes and system 160 of coordinates.

FIG. 4B shows a design 170 that was automatically produced from thedesign 150 with the aid of the method explained below with reference toFIG. 8. The position of the lines 152 and 154 has not changed. Bycontrast, a circle 156 a has been displaced in the y direction incomparison with the circle 156 such that its edge has a largest ycoordinate corresponding to the y coordinate of the line 152. On accountof the displaced circle 156 a, there is an overlap region 172 at whichthe circle 156 a overlaps the interspace between the straight line 152and the dashed straight line 154. This overlap leads to an overlapbetween the interconnect liner and the via liner in the case of aninterconnect/contact hole arrangement produced in accordance with thedesign 170.

FIG. 5A shows a design 180 for the arrangement of a contact holerepresented by a circle 182 at the end of a pattern formed by straightlines 184, 186 and 188 arranged in U-shaped fashion. The circle 182 issituated in the center of a region enclosed by the straight lines 184 to188 and has a diameter D4 that is approximately one third smaller than awidth B9 of the pattern that corresponds to the distance between thestraight lines 184 and 188 running parallel to one another. In thedesign 180, there are no overlap regions between the circle 182 and adashed line 190 representing the position of the interconnect liner.

FIG. 5B shows a design 200 that was automatically produced from thedesign 180. The position of the lines 184 to 188 has remained unchanged.However, the circle 182 has been displaced in the x direction to producea circle 182 a. The largest x coordinate of the circle 182 a correspondsto the x coordinate of the straight line 186, which specifies theposition of the end side of the pattern. An overlap region 202 resultsbetween the circle 182 a and the region lying between the dashed line190 and the straight line 186.

FIG. 5C shows a design 210 that was automatically produced from thedesign 180 in the case of an alternative method. The position of thestraight lines 184, 186 and 188 has remained unchanged. However, thecircle 182 has been displaced both in the x direction and in the ydirection to produce a circle 182 b. The largest x coordinate of thecircle 182 b corresponds to the x coordinate of the straight line 186.The largest y coordinate of the circle 182 b corresponds to the ycoordinate of the straight line 184. As a result, there are two overlapregions 212 and 214 between the circle 182 b and the region lyingbetween the line 190 and the straight line 184 and respectively thestraight line 186. The design 214 was produced for example by successiveapplication of rules for shifting the circle 182 in the x direction andin the y direction.

FIG. 6A shows a design 220 containing straight lines 222, 224 and 226that are arranged in U-shaped fashion and ultimately predefine theposition of the edge of a trench for an interconnect. A distance betweenthe straight lines 222 and 226 that lie parallel to one another definesa width B10 of the pattern formed by the straight lines 222, 224 and226. Moreover, the design 220 contains a circle 228 which ultimatelypredefines the position of a contact hole. A dashed line 230 shows theposition of an interconnect liner with regard to the design 220. In thedesign 220, there are already two overlap regions 232 and 234, in whichthe circle 228 overlaps the region between the line 222 and the dashedline 230 and between the line 226 and the dashed line 230. The circle232 has a diameter D5 that is equal to the width B10. By contrast, thereis no overlap region at the end of the pattern formed by the straightlines 222 to 226, i.e. in the region of the straight line 224.

FIG. 6B shows a design 240 that was automatically produced from thedesign 220. The position of the straight lines 222 to 226 has remainedunchanged. However, the circle 228 has been displaced in the x directionto produce a circle 228 a. The largest x coordinate of the circle 228 acorresponds to the x coordinate of the straight line 224. Accordingly,in addition to the overlap regions 232 and 234, in the design 240, thereis a third overlap region 242 at the end side of the trench representedby the straight lines 222 to 226. The number of overlap regions has thusbeen increased by the application of the automatic method.

FIG. 7 shows a design 250, in which there are four overlap regions 252,254, 256 and 258 between a circle 260 and regions between the straightlines 262, 264, 266 and 268 forming a square and a dashed line 270. Thecircle 260 has a diameter D6. The square has a side length B11 and B12,respectively, which is equal to the diameter D6. The design 250 waslikewise produced automatically with the aid of the method explainedbelow with reference to FIG. 8. The distance between the straight lines252 and 256 and between the straight lines 254 and 258 was reduced inthis case.

FIG. 8 shows method steps of a method for increasing the number ofcontact locations of via liner and interconnect liner in an integratedcircuit arrangement in a targeted manner. The method begins in a methodstep 300. In a subsequent method step 302, design data are predefined,said design data being stored for example in accordance with astandardized data format, e.g. in accordance with the format GDSII(graphic design system), which is utilized e.g. by the program CadenceFramework. The design data are stored in a file and predefine a bitpattern or a vector graphic for different design planes.

In a method step 304, rules according to which the design data areintended to be changed are predefined. The rules are stored in aprogram, for example, which changes the geometrical patterns of thedesign in the manner of an image editing program.

In a method step 306, a first contact location between a via and aninterconnect is determined, which is predefined by the design data. In asubsequent method step 308, a check is made to ascertain whether analteration in accordance with the predefined rules is possible for acontact location that has been determined, i.e. in the exemplaryembodiment:

-   -   whether a constriction of an interconnect is possible, or    -   whether a displacement of a contact hole for a via or a        displacement of an interconnect is possible.

In the exemplary embodiment, firstly a check is made to ascertainwhether a constriction is possible. If this is the case, then the designdata are correspondingly changed in a method step 310 that directlysucceeds method step 308. In a subsequent method step 312, a check ismade to ascertain whether, at the contact location determined, a furtherrule leads to an increase in the number of overlap regions or ultimatelycontact regions. If this is the case, then the method is continued withmethod step 308. The method is then in a loop comprising the methodsteps 308 to 312. This loop is left in method step 312 only when it isascertained that there is no longer any further rule that might lead, inaccordance with the predefined rules, to an improvement in the designfor the contact location determined. In this case, a method step 314directly succeeds method step 312.

Method step 314 also directly succeeds method step 308 if it isascertained in said method step 308 that no alteration is possible inaccordance with a rule.

In method step 314, a check is made to ascertain whether there arefurther unprocessed contact locations in accordance with the originaldesign data. If this is the case, then method step 306 directly succeedsmethod step 314 again. The method is thus in a method loop comprisingthe method steps 306 to 314. In the course of performing method steps308 to 314 in this method loop, gradually all the contact locations ofthe design are checked and, if appropriate, the design data for thecontact locations are changed in accordance with the predefined rules.The loop comprising method steps 308 to 314 is left in method step 314only when there are no further contact locations in accordance with thedesign that have not yet been checked and, if appropriate, changed. Inthis case, a method step 316 directly succeeds method step 314.

In method step 316, the changed design data are stored in a file and arethus available for further processing, for example for the production ofmasks for producing the integrated circuit arrangement. As analternative or in addition, the changed design data are output, forexample as a graphical representation on a screen. A developer then hasthe opportunity to test samples of the changes that have been carriedout. The method is ended in a method step 318.

FIG. 9 shows an apparatus 320 for performing method steps 300 to 318explained with reference to FIG. 8. The apparatus 320 contains apredefinition unit 322 for design data, a predefinition unit 324 for therules, a control unit 326, a change unit 328 and a memory unit 330, e.g.a RAM (random access memory). The predefinition units 322 and 324, thecontrol unit 326 and the change unit 328 access the memory unit 330 viaa memory bus 332. The control unit 326 controls the operations in thepredefinition unit 322, in the predefinition unit 324 and in the changeunit 328, see arrows 334 to 338.

The predefinition unit 322 serves for predefining the design data, i.e.for performing method step 302. The predefinition unit 324 serves forstoring rules, i.e. for performing method step 304. The change unit 328serves for changing the design data in accordance with the rulespredefined by the predefinition unit 324.

An input unit 340, e.g. a keyboard, an output unit 342, e.g. a screen,and a floppy disk drive 344 are additionally connected to the apparatus320 via a line 346, 348 and 350, respectively.

In one exemplary embodiment, the functions of the units 322 to 328 areimplemented by electronic switching mechanisms that do not contain aprocessor. In an alternative exemplary embodiment, the functions of theunits 322 to 328 are implemented with the aid of a processor 352 thatprocesses a program in a program memory unit in a program memory unit354, see arrow 356.

1. An integrated circuit arrangement comprising: at least onemetallization layer containing a multiplicity of electrically conductiveinterconnects; an interconnect dielectric between the interconnects;electrically conductive interconnect intermediate material arranged ineach case between a side area of an interconnect and the interconnectdielectric; a multiplicity of electrically conductive connectingsections which in each case form a section of an electrically conductiveconnection to or from an interconnect; a connecting section dielectricbetween the connecting sections; and connecting section intermediatematerial arranged in each case at least one of between a connectingsection and the connecting section dielectric and between a connectingsection and an interconnect, wherein the interconnect intermediatematerial and the connecting section intermediate material makes contactwith one another at at least one connection.
 2. The circuit arrangementas claimed in claim 1, wherein at least one of: at the connection, theinterconnect intermediate material and the connecting sectionintermediate material make contact at two or three or four side areas ofan interconnect; and the interconnect intermediate material and theconnecting section intermediate material make contact at an edge formedby a contact line of two side areas of the interconnect.
 3. The circuitarrangement as claimed in claim 1, wherein at least two sections of thesame interconnect or of different interconnects are wider than theconnecting sections at the connecting sections, and wherein the contactregions are situated at side areas of the sections whose normaldirections are situated transversely or oppositely with respect to oneanother.
 4. The circuit arrangement as claimed in claim 1, wherein atleast one of: the interconnect comprises copper, a copper alloycontaining at least ninety-five percent copper, aluminum, or an aluminumalloy containing at least ninety-five percent aluminum, at least one ofthe interconnect dielectric and the connecting section dielectriccontains an oxide or a dielectric having a dielectric constant of lessthan 3.9, at least one of the interconnect intermediate material and theconnecting section intermediate material contains a nitride, theinterconnect intermediate material contains a refractory metal, and theconnecting sections contain tungsten or copper.
 5. The circuitarrangement as claimed in claim 4, the oxide comprises contains silicondioxide.
 6. The circuit arrangement as claimed in claim 4, wherein thenitride comprises a metal nitride.
 7. The circuit arrangement as claimedin claim 4, wherein the refractory metal comprises tantalum.
 8. Thecircuit arrangement as claimed in claim 1, wherein at least one of: anarea of an interconnect that is adjacent to a connecting section is thaneighty percent free of an electrically conductive intermediate material,and the circuit arrangement has been fabricated by means of a damascenetechnique or by means of a dual damascene technique.
 9. An integratedcircuit arrangement comprising: at least one metallization layercontaining a multiplicity of electrically conductive interconnects; aninterconnect dielectric between the interconnects; electricallyconductive interconnect intermediate material arranged in each casebetween a side area of an interconnect and the interconnect dielectric;a multiplicity of electrically conductive connecting sections which ineach case form a section of an electrically conductive connection to orfrom an interconnect; a connecting section dielectric between theconnecting sections; and connecting section intermediate materialarranged in each case at least one of between a connecting section andthe connecting section dielectric and between a connecting section andan interconnect, wherein the interconnect intermediate material and theconnecting section intermediate material makes contact with one anotherat at least one connection, wherein at least one of: the interconnecthas a constriction at the connecting section, the width of saidconstriction being chosen such that contact regions are produced atopposite side areas of the interconnect, and the constriction, along thelongitudinal axis of the interconnect, has a length that is less thanfive times or less than three times the width of the constriction. 10.The circuit arrangement as claimed in claim 9, wherein at least one of:the connecting section is arranged at an end of the interconnect, andthe constriction has the form of a wedge or the form of a step.
 11. Thecircuit arrangement as claimed in claim 9, wherein at least one of: theinterconnect extends in at least two different directions from theconnecting section, and each end of the constriction has the form of awedge or the form of a step.